As a method for manufacturing an SOI wafer, it has been mainly performed a process in which an ion implanted layer for delamination is formed by implanting mainly hydrogen ions into a bond wafer to form an SOI layer, and the bond wafer is bonded with a base wafer via an insulation film, followed by delaminating the bond wafer along the ion implanted layer for delamination to form a thin film (ion implantation delamination method). This process, however, induces defects on the periphery in delaminating the bond wafer. As a solution for such defects on the periphery, it is known to form a sag shape (a shape which has a positive roll-off amount) at the outermost peripheral portion on the side to which a wafer for bonding (a bond wafer and a base wafer) is bonded (Patent Document 1).
In manufacturing an epitaxial wafer, the outermost peripheral portion tends to be a rise shape (a shape which has a negative roll-off amount) when an epitaxial layer is formed on a substrate for epitaxial growth (also referred to as an epi-sub). Accordingly, it has been desired to control the flatness after forming an epitaxial layer by previously forming a sag shape at a portion to be formed the rise shape on the substrate for epitaxial growth.
Accordingly, in prior manufacturing of the wafer for bonding and the substrate for epitaxial growth, the polishing time has been extended in the step of polishing a main surface of a wafer to form a sag shape. In such a method, however, the shape of an internal side from the outermost peripheral portion is degraded by extending the time for polishing a main surface of the wafer to form the sag shape. The degradation of a shape in this context is expressed by an SFQRmax value, which is the maximum value of flatness SFQR (Site Front least sQuares Range), for example, and larger SFQRmax value means that the shape of the internal side from the outermost peripheral portion is degraded more severely. Generally, smaller flatness SFQRmax is preferable since large SFQRmax causes degradation of defocus in a device process. Accordingly, it has been desired a method that can form a desired sag shape with high accuracy without deforming the shape of the internal side from the outermost peripheral portion (without increasing the flatness SFQRmax).
As a solution for the foregoing problem, Patent Document 2 describes a method for manufacturing a substrate for epitaxial growth without extending time for polishing a main front surface of a semiconductor wafer to form a sag shape. Specifically, this method is a method as shown in FIGS. 13 (a) and (b), in which each of the quartered regions of a semiconductor wafer 101 including a chamfered portion 108 composed of a chamfered surface on the front surface side 102, a chamfered surface on the back surface side 103, together with an end face, and an outermost peripheral portion adjacent to the chamfered surface on the back surface side 103 is polished with a polishing apparatus provided with four respective polishing pads (a polishing pad 104 for the chamfered surface on the front surface side, a polishing pad 105 for the chamfered surface on the back surface side, a polishing pad 106 for the end face, and a polishing pad 107 for the outermost peripheral portion on the back surface). This can form a sag shape while mirror-polishing the chamfered portion 108. Although such a method can polish the quartered regions adjacent to the chamfered portion at once, it makes the end shape of the chamfered portion of the semiconductor wafer 101 (the shape of the end face 109) be sharp as shown in FIG. 15. When a wafer processed by this method is used as a wafer for bonding, for example, stress concentration occurs at the tip end of the chamfered portion to cause faults of frequent breakage when centrifugal force occurs in ion implantation of a subsequent step.